Subject: Re: SDL-News: Exact semantics of OUTPUT
From: yves Lejeune (lejeune#tlse.verilog.fr )
Date: Wed Jun 10 1998 - 15:57:55 GMT
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-----From lejeune#tlse.verilog.fr (yves Lejeune) to sdlnews -----
> -----From "A. Hirche" <hirche#informatik.uni-essen.de> to sdlnews -----
> I am trying to get through the semantics of the output statement but are
> stuck with the meaning of the VIA / VIA ALL constructs. I looked into
> Z100, Z100-F3, Ellsberger/Hogrefe/Sarma: SDL and
> Olsen/Faergemand/Moeller-Pedersen/Reed/Smith: Systems Engineering Using
> SDL-92, but was not quite satiesfied with the explanations offered
> there.
> So could someone please sort this out once and for all :-)?
> I have included a small specification to demonstrate what I THINK should
> happen and where the problem lies. Pointing out any misconceptions on my
> side is greatly appreciated.
>
To understand the meaning of the VIA / VIA ALL constructs,
I had to read Annex F.3 of Z.100, the core Z.100 alone was
not enought.
The important function is handle-send-signal() [4.1.1.8],
and the folowing auxiliary functions.
> Now consider replacing the comment /* HERE */ in p1 with one of the
> following:
>
> (0) output s1;
> Signal s1 may take any route that takes it to a possible receiver, in
> this case one of the eight possible routes from p1 to p2, which are:
> sr1->ch1->sr3
> sr1->ch1->sr4
> sr1->ch2->sr3
> sr1->ch2->sr4
> sr2->ch1->sr3
> sr2->ch1->sr4
> sr2->ch2->sr3
> sr2->ch2->sr4
I agree. Furthermore if you had specified "signalset s1" in process p1,
there would be one more communication path which is the
empty set, used for output to instances of the same process.
>
> (1) output s1 via sr1;
> s1 may only take pathes passing through sr1, thus leaving it with four
> possibilities.
>
> (2) output s1 via sr1, ch1;
> The number of choices is reduced even more, leaving s1 with only two
> possible choices.
No, the set "sr1, ch1" does not mean "sr1 and ch1", but "sr1 or ch1".
This is specified by the is-in-via() function.
In fact in the concrete grammar <via path> is badly named,
as it does not represent one communication path,
but a set of possible endpoints of communication pathes.
Well in fact it is not really a set of endpoints,
as you can specify for instance the channel ch1 which is not an endpoints,
you just specify it as a starting point.
So here as sr1 goes to ch1, "output s1 via sr1, ch1"
is the same as just "output s1 via ch1", and possible communication pathes are
all the pathes which go trough ch1:
sr1->ch1->sr3
sr1->ch1->sr4
sr2->ch1->sr3
sr2->ch1->sr4
>
> (3) output s1 via sr1, ch1, sr3;
> This is an error, as none of the Signal-route-pathes of sr3 originates
> from p1.
> Is there a reason why it is not allowed to give the full path in SDL?
In fact you can not reference sr3 in process p1, as it is not visible.
> (4) output s1 via all;
> This should result in a total of eight signals arriving at p2, with each
> signal taking a distinct path.
You can not write "via all" alone, the list of <via path> is not optionnal.
> (5) output s1 via all sr1, ch1;
> Under Model, the Z100 says "Stating via all is derived syntax for
> multicasting the signal via the communication paths mentioned in <via
> path>, so that signals are sent in the same order as <via path element>s
> appear in <via path>, one via each <via path element>."
> Does this mean, that (4) is equivalent to
> a) output s1 via all sr1;
> output s1 via all ch1;
> i.e. (4) is a shorthand for two separate outputs,
Yes, and more precisely:
output s1 via sr1;
output s1 via ch1;
> resulting in a total of 8 signals arriving at p2,
No, the are only two signals arriving at p2, one for each output.
In fact "via all" is presented as a multicast, not a broadcast mechanism.
> b) sending two instances of s1, one taking the path sr1->ch1->sr3
> and the other taking the path sr1->ch1->sr4.
No, see comments about (2) above : <via path> is not a communication path.
> Thanks for taking the time to read all this :-)
>
I hope this helps,
Best regards,
Yves.
Yves Lejeune
VERILOG SA
150, rue Nicolas Vauquelin - BP 1310
31106 Toulouse Cedex - France
Tel : +33 5 61 19 29 39
Fax : +33 5 61 40 84 52
e-mail : lejeune#verilog.fr
http://www.verilogusa.com
-----End text from lejeune#tlse.verilog.fr (yves Lejeune) to sdlnews -----
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